
--------------------------------------------------------------------------------
-- Company: 
-- Engineer:
--
-- Create Date:   12:15:40 04/23/2012
-- Design Name:   RegistroPC
-- Module Name:   C:/Xilinx92i/pc/testbench_pc.vhd
-- Project Name:  pc
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: RegistroPC
--
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends 
-- that these types always be used for the top-level I/O of a design in order 
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY testbench_pc_vhd IS
END testbench_pc_vhd;

ARCHITECTURE behavior OF testbench_pc_vhd IS 

	-- Component Declaration for the Unit Under Test (UUT)
	COMPONENT RegistroPC
	PORT(
		PC_IN : IN std_logic_vector(9 downto 0);
		loadEnable : IN std_logic;
		clk : IN std_logic;
		reset : IN std_logic;          
		PC_OUT : OUT std_logic_vector(9 downto 0)
		);
	END COMPONENT;

	--Inputs
	SIGNAL loadEnable :  std_logic := '0';
	SIGNAL clk :  std_logic := '0';
	SIGNAL reset :  std_logic := '0';
	SIGNAL PC_IN :  std_logic_vector(9 downto 0) := (others=>'0');

	--Outputs
	SIGNAL PC_OUT :  std_logic_vector(9 downto 0);

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: RegistroPC PORT MAP(
		PC_IN => PC_IN,
		loadEnable => loadEnable,
		clk => clk,
		reset => reset,
		PC_OUT => PC_OUT
	);


	clk_tb: PROCESS
	BEGIN
		wait for 50 ns;
		clk <= '1';
		wait for 50 ns;
		clk <= '0';
		
	END PROCESS;


	tb : PROCESS
	BEGIN
		reset <= '1';
		loadEnable <= '0';
		
		wait for 100 ns;
		reset <= '0';
		loadEnable <= '1';
		PC_IN <= "0000000011";
		
		wait for 100 ns;
		loadEnable <= '0';
		
		wait for 100 ns;
		loadEnable <= '1';
		PC_IN <= "0000011111";

		wait for 100 ns;
		loadEnable <= '0';
				
		wait for 100 ns;
		loadEnable <= '1';
		PC_IN <= "1100000011";

		
		wait; -- will wait forever

	END PROCESS;

END;
